Memory cells of dynamic random access memories (DRAMs) generally comprise a storage capacitor and a select transistor. An information item in the form of an electric charge which represents a logic 0 or a logic 1 is stored in the storage capacitor. Driving the read or select transistor via a word line allows the information item stored in the storage capacitor to be read via a bit line. The storage capacitor has to have a minimum capacitance if the charge is to be reliably stored and if it is to be possible to distinguish the information item which is read. The lower limit for the capacitance of the storage capacitor is therefore considered to be approximately 25 fF.
FIG. 1 diagrammatically depicts the circuit diagram of a DRAM memory cell 42 having a storage capacitor 9 and a select transistor 10. The select transistor 10 is preferably designed as a normally off n-channel field-effect transistor (FET) and has a first n-doped source/drain electrode 18 and a second n-doped source/drain electrode 19, between which is arranged an active, weakly p-conducting channel region 23. Above the channel region 23 is a gate insulator layer, above which is arranged a gate electrode 17 which can be used to influence the charge density in the conductive channel region 23.
The first source/drain electrode 18 of the select transistor 10 is connected to the second electrode 8 of the plate-type capacitor 9 via a connecting region 21, 43. A first electrode 6 of the storage capacitor 9 is in turn connected to a capacitor plate 55, which is preferably common to all the storage capacitors of a DRAM memory cell array.
The second source/drain region 19 of the select transistor 10 is connected to a bit line 38 via a bit line contact 37. The information stored in the storage capacitor 9 in the form of charges can be written and read via the bit line. A write or read operation is controlled by a word line 33, which is connected to the gate electrode 17 of the select transistor 10, with a current-conducive channel being produced in the conductive channel region 23 between the first source/drain region 18 and the second source/drain region 19 by the application of a voltage. To prevent charging of the semiconductor substrate during the operations of switching the transistor on and off, a substrate terminal 58 is also provided.
Since the storage density is increasing from one memory generation to the next, the surface area required by the single-transistor memory cell needs to be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor needs to be maintained.
Up to the 1 MBit generation, both the read transistor and the storage capacitor are realized as planar components. From the 4 MBit memory generation onward, a further reduction in the surface area of the memory cell is achieved by using a three-dimensional arrangement of the storage capacitor. One possible option is to realize the storage capacitor in a trench. In this case, by way of example, a diffusion region which adjoins the wall of the trench and a doped polysilicon filling in the trench act as electrodes of the storage capacitor. The electrodes of the storage capacitor are therefore arranged along the surface of the trench. This increases the effective surface area of the storage capacitor, on which the capacitance is dependent, compared to the space taken up for the storage capacitor at the surface of the substrate, which corresponds to the cross section of the trench. The packing density can be increased further by reducing the cross section of the trench while at the same time increasing its depth.
FIG. 2 shows a diagrammatic cross section through two memory cells each having a trench capacitor. In FIG. 2, a first capacitor electrode 6, which is usually realized by a highly n-doped region, a dielectric layer 7 and a second capacitor electrode 8, which is usually realized as a polysilicon filling, are arranged in a lower trench region. An isolation trench 14 made from SiO2, which is intended to suppress a parasitic transistor which would otherwise form at this location, is formed in an upper trench region. The interior of the trench is in turn filled with an n-doped polysilicon filling. The adjacent capacitor trenches are isolated from one another by an isolation trench 57. The inner capacitor electrode 8 of each trench capacitor is connected to a first n-doped source/drain region 18 of the select transistor via an n+-doped region 21 (buried strap). The second source/drain region 19 is in each case also realized by an n-doped region within the semiconductor substrate and is connected to the associated bit line 38 via a bit line contact 37. A gate electrode 17 comprises a polysilicon layer 17a, a silicide layer 17b (e.g., WSi) and an Si3N4 layer 17c. The first capacitor electrodes 6 are connected to one another via what is known as a buried plate 55. The substrate terminal 58 is provided by the p-doped region 58. In the illustration shown in FIG. 2, the select transistor 10 is designed as a planar select transistor in the substrate surface 1, in which the current flows in the horizontal direction between the first and second source/drain regions 18, 19.
Furthermore, the storage capacitor may be formed as a stacked capacitor on the substrate surface 1.
Given the ever smaller surface areas of the memory cells caused by increasing miniaturization, maintaining the current driver capacity of the transistor represents an increasing problem. The term current driver capacity of the transistor is to be understood as meaning the ability of the transistor to deliver a sufficient current to charge the storage capacitor quickly at a predetermined source/drain potential and a predetermined gate voltage. However, the reduction in the size of the cell surface areas and the resultant reduction in the transistor dimensions reduce the transistor width of the planar surface transistors. This in turn leads to a reduction in the current which is connected through from the transistor to the storage capacitor.
One possible short-channel surface transistor concept which can be used to solve this problem is what is known as the double-gate transistor, in which the channel region between source and drain regions is surrounded by a gate electrode on at least two sides, with the result that a high current driver capacity can be achieved even with very short channel lengths, since the channel width is increased compared to conventional planar select transistors. In this case, it is preferable for the double-gate transistor to be designed as what is known as a fin-FET, in which the channel region is designed in the form of a fin between the source and drain regions and the channel region is surrounded by the gate electrode at least on the two opposite sides. Given a suitable configuration of the fin width and therefore of the channel width, a fin-FET of this type can be operated in such a way that in the connected-through state with a gate electrode voltage applied, the two inversion layers which form beneath the gate electrodes overlap, and consequently a complete charge carrier inversion takes place, with the result that the entire channel width can be used to carry current. Furthermore, with fin-FETs, there is the possibility of using the gate potential to directly control what are known as the short-channel effects, which occur with very short channel lengths and can lead to a change in the threshold voltage of the transistor. Furthermore, fin-FETs are distinguished by a high subthreshold swing and therefore good switch-on and switch-off properties combined, at the same time, with a reduced subthreshold leakage current.
When fabricating the memory cell shown in FIG. 2, it is usual for the gate electrodes 17 and the word lines to be produced in one step from one material and at the same vertical distance from the substrate surface. Accordingly, passive word lines (passing word lines, PWLs) 56, which in each case act as gate electrodes in the select transistors located in the plane behind the two trench capacitors, are in each case arranged above the two trench capacitors 9. Conversely, the gate electrodes 17 shown in the select transistor 10 of the present plane are what are known as active word lines, whereas in the memory cells of the plane behind they act as passive word lines. More accurately, in a cross section arranged behind the plane of the drawing illustrated, they run directly over the trench capacitors 8 behind.
Passive word lines of this type are disadvantageous in that they prevent access to the trench capacitors after the latter have been formed, making it in particular impossible to realize the contact between second capacitor electrode and first source/drain region 18 as a surface terminal. As shown in FIG. 2, this terminal 21 is realized as a buried strap, i.e. a doped region buried in the substrate, which can result, for example, in problems with out diffusion of the doped regions. Furthermore, there has to be a minimum distance between the highly doped regions 21 and 18 in order to minimize the extent to which these regions influence one another. Finally, a buried strap terminal is more complex to produce.
A further drawback of the passive word lines 6 arranged above the trench capacitors 8 is that it is necessary to avoid a short circuit between the corresponding polysilicon layers 17a and the n+-doped region 22 below. These drawbacks in particular make further miniaturization of the memory cell difficult.